1. Field of the Invention
The present invention relates to an integrated analog-to-digital converter (hereinafter called “integrated AD converter”) which is adaptable to a solid state imaging device typified by a CMOS image sensor, a solid state imaging device, and a camera system.
2. Description of the Related Art
There has been proposed an integrated AD converter mountable in, for example, a solid state imaging device which performs high-resolution imaging (see JP-A-2008-92091 (Patent Document 1)).
Patent Document 1 has proposed an integrated AD converter which enhances the resolution without increasing the clock frequency.
This integrated AD converter acquires information on lower bits by means of a time quantizer (TDC: Time-to-Digital Converter) which latches and decodes clock signals of different phases using an ordinary high-bit counter and ring oscillator, thereby enhancing the resolution without increasing the clock frequency.
FIG. 1 is a diagram showing the configuration of the AD converter disclosed in Patent Document 1.
This AD converter 1 has a comparator 2, a TDC (time quantizer, latch and decoder) 3, a high-bit counter 4, and a transfer bus 5.
The AD converter 1 in this example is an integrated AD converter which uses four clock signals of phases different from one another by 45 degrees, and has a resolution of a total of fourteen bits including eleven bits for the high-bit counter and three bits for the low-bit TDC 3.
The comparator 2 compares an input voltage VSL with a reference voltage RAMP with a ramp waveform whose voltage value linearly changes with time, and outputs the comparison result as a signal VCO.
The high-bit counter 4 starts or stops the operation at a timing at which the signal VCO is changed, and the low-bit TDC 3 latches information on clock signals of different phases.
FIG. 2 is a diagram showing the principle of the low-bit TDC which provides a higher resolution than the clock frequency.
When the values of four clock signals CLKA, CLKB, CLKC and CLKD whose phases differ from one another by 45 degrees are latched at a timing at which the signal VCO changes in one cycle of the clock frequency, eight extending codes EB [3:0] are obtained.
Lower-bit information of three bits can be acquired by decoding the eight extending codes by means of the latch and decoding section of the TDC 3.
This example is a post counting type in which the high-bit counter 4 starts counting at the timing at which the signal VCO changes.
FIG. 3 is a diagram showing changes in binary values of the extending codes EB [3:0] obtained when the timing at which the signal VCO changes is changed around the edge of each clock, and decoding results.
Normally, a change in a decoded value is ±1 LSB and is sequential. However, an error of ±7 LSB occurs around the rising edge of the clock signal CLKA, depending on the connection to the high-bit ripple counter. This error is called “sparkle error”.
FIGS. 4A and 4B are diagrams showing a case where proper counting is carried out consecutively at the joint portion of the high-bit counter and the low-bit TDC, and a case where a sparkle error occurs at that joint portion.
The clock signal CLKA serves as the clock signal for the high-bit counter 4 and the clock signal for the low-bit TDC 3.
A sparkle error may occur when the signal VCO changes around the rising edge of the clock signal CLKA.
When the signal VCO changes slightly before the rising edge of the clock signal CLKA, [0000b] is stored as the extending code EB [3:0], and when the high-bit counter 4 counts immediately thereafter at the rising edge of the clock signal CLKA, it is the proper counting.
When the signal VCO changes slightly after the rising edge of the clock signal CLKA, [1000b] is stored as the extending code EB [3:0].
It is also the proper counting when the high-bit counter 4 does not count immediately before the rising edge of the clock signal CLKA, and waits for the next rising edge.